1. Field of the Invention
The present invention relates to a system for controlling a repeated processing or execution of one or more instructions (called a "loop processing") in a data processing system, and more specifically to a stack management system for a saving and a restoring in the loop processing.
2. Description of Related Art
In the prior art, a loop instruction having no branch overhead is widely used in digital signal processors.
For example, the digital signal processor available under the tradename "320C30" from Texas Instruments has a loop instruction. However, the processor 320C30 does not pay consideration to a nesting. Therefore, if a second loop instruction is executed in the course of execution of a first loop instruction, variable information such as the number of loops, a loop head address, etc. used for control of the first loop is broken.
The digital signal processors available under the tradename "DSP56001" and "DSP96002" from MOTOROLA have a loop instruction having the specification capable of realizing the nesting. When this loop instruction is executed, plural items of information such as the number of loops and the loop head address are set in corresponding registers, respectively, and the contents previously set in the corresponding registers are saved into a separately provided hardware stack.
On the other hand, in the case of describing a two-dimensional data processing by the loop instructions, particularly in the case of accessing a rectangular area processing in an image signal processing, it is preferred to be able to realize the nesting.
Here, one example of the loop processing will be briefly described. When a loop instruction is executed, a loop counter, a loop end address register and a loop start address register are set. Then, a group of instructions included in the loop are sequentially executed. If a value of a program counter reaches an address just before a loop end address, a loop head branch flag is set, so that a next instruction is not executed, and the instruction jumps to the head of the loop. This jump to the head of the loop is executed by transferring a value of the loop start address register to the program counter.
This jump is repeated for the designated number of loops. The value set in the loop counter is decremented by "1" each time the jump occurs. When the value of the loop counter becomes zero, a loop end flag is set, so that the jump no longer occurs, and the operation goes out of the loop.
As mentioned above, the loop counter, the loop end address register and the loop start address register hold a fundamental condition when the loop is executed. If the loop is nested, it is necessary to save and restore the information held in the loop counter, the loop end address register and the loop start address register.
In the conventional digital signal processor, the saving and restoring of the information held in the loop counter, the loop end address register and the loop start address register are realized by transferring information between the loop counter, the loop end address register and the loop start address register and a hardware stack which is provided separately from the loop counter, the loop end address register and the loop start address register and which is provided in common to the loop counter, the loop end address register and the loop start address register and also to other functions.
Namely, when a loop instruction is being executed, if another loop instruction is executed, the contents of the loop counter, the loop end address register and the loop start address register are pushed or transferred to the common hardware stack. When the loop end condition for the second loop is satisfied and the operation goes out of the second loop, the contents of the common hardware stack are popped or restored to the loop counter, the loop end address register and the loop start address register, respectively, so that the first loop is restarted from a point where the nesting occurs.
Ordinarily, it is a general rule in the digital signal processor that a throughput of an instruction execution is one clock.
At a loop starting point, it is possible to control to the effect that the loop instruction itself is executed with a plurality of clocks. Therefore, no problem occurs. On the other hand, when a loop ending condition is satisfied, no loop ending instruction exists. However, the contents of the common hardware stack must be popped into or restored to the loop counter, the loop end address register and the loop start address register, respectively. This processing cannot be executed in only one clock. In other words, during a period of transferring the contents of the common hardware stack into to the loop counter, the loop end address register and the loop start address register, respectively, a plurality of instructions are executed in parallel.
In general, the common hardware stack is used not only for the loop processing but also for the saving and restoring of the status in subroutine callings, interrupt processings and exception processings. However, for a period during which the contents of the common hardware stack are transferred into the loop counter, the loop end address register and the loop start address register, it is not possible to write an instruction (for example, a subroutine call instruction, a return instruction, a loop instruction, etc.) using the common hardware stack. In addition, continuous loop endings are not permitted. In other words, a great restriction concerning the loop ending is encountered in describing or preparing a program.
Furthermore, there is a possibility that the common hardware stack underflows, and an extra hardware logic for controlling this exception processing is also required.
As seen from the above, when the loop instruction is executed, if the status is saved using only one hardware stack, various disadvantages are encountered. Namely, extra timing clocks are required at the time of restoring the status. The programming is subjected to the above mentioned restriction, and an additional control logic for the exception processing is inevitably required.